09:1609:16, 8 November 2020diffhist−49
Template:AMD Ryzen 5000 Series
Correct/clarify L3 cache specs: per the table, the first two only have one CCD, so a spec "per CCD" is superfluous/confusing, whilst the latter two have "32 MiB per CCD", not "2 x 32 MiB per CCD" (which would be "64 MiB per CCD"). Chose that rather than plain 64 MiB for consistency with L2 cache and provision of more information.Tags: Mobile editMobile web edit
10:3410:34, 16 November 2019diffhist−11
Scarlett Moffatt
Remove "allegedly": seems pretty uncontroversial as there are citations showing she fulfilled presenting roles.Tags: Mobile editMobile app editAndroid app edit