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  • 09:16 09:16, 8 November 2020 diff hist −49 Template:AMD Ryzen 5000 SeriesCorrect/clarify L3 cache specs: per the table, the first two only have one CCD, so a spec "per CCD" is superfluous/confusing, whilst the latter two have "32 MiB per CCD", not "2 x 32 MiB per CCD" (which would be "64 MiB per CCD"). Chose that rather than plain 64 MiB for consistency with L2 cache and provision of more information. Tags: Mobile edit Mobile web edit

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