included a
DMA controller, interrupt controller, timers, and
chip select logic. A small number of additional instructions. The
80188 was a version with an 8-bit bus.
first
x86 processor with
protected mode including segmentation based virtual memory management. Performance improved by a factor of 3 to 4 over 8086. Included instructions relating to protected mode. The
80286 had a 24-bit address bus.
first
32-bitx86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
Intel's second generation of
32-bitx86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support
micro-op fusion and smart cache.
commonly referred to as P7 although its internal name was P68 (P7 was used for
Itanium). Used in
Pentium 4,
Pentium D, and some
Xeon microprocessors. Very long
pipeline. The
Prescott was a major architectural revision. Later revisions were the first to feature Intel's
x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the
NX (No eXecute) bit to implement
executable-space protection.
reengineered P6-based microarchitecture used in
Intel Core 2 and
Xeon microprocessors, built on a 65 nm process, supporting
x86-64 level SSE instruction and
macro-op fusion and enhanced
micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher
FSB and clock speeds,
SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.
released November 17, 2008, built on a 45 nm process and used in the
Core i7,
Core i5,
Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions,
SSE4.2.
Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007.[2] First x86 to introduce 256 bit
AVX instruction set and implementation of YMM registers.
Ivy Bridge: successor to Sandy Bridge, using 22 nm process, released in April 2012.
22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including
AVX2 and
FMA.
Broadwell: 14 nm derivative of the Haswell microarchitecture, released in September 2014. Three-cycle FMUL latency, 64 entry scheduler. Formerly called Rockwell.
Kaby Lake: successor to Skylake, released in August 2016, broke Intel's
Tick-Tock schedule due to delays with the 10 nm process.
Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes)[3]
Whiskey Lake: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities)[3]
Skylake-X: high-end desktop, workstation and server microarchitecture, released on June 19, 2017 (HEDT), July 11, 2017 (SP) and August 29, 2017 (W). Introduces support for
AVX-512 instruction set.
Coffee Lake: successor to Kaby Lake, using 14++ nm process, released in October 2017
Comet Lake: successor to Coffee Lake, using 14++ nm process, released in August 2019[4]
Cooper Lake: server-only, optimized for
AI oriented workloads using
bfloat16, with limited availability only to Intel priority partners, using 14++ nm process, released in 2020[5][6]
After releasing the Palm Cove core, Intel has changed their microarchitecture naming scheme, decoupling the CPU cores from their manufacturing nodes.[7][8] Successor to Skylake (canceled), includes the
AVX-512 instruction set.[9][10]
Cannon Lake: mobile-only successor of Kaby Lake, using Intel's 10 nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019.[11]
Successor to the Palm Cove core, first non-Atom core to include hardware acceleration for
SHA hashing algorithms.[12]
Ice Lake: low power, mobile-only successor to Whiskey Lake, using 10 nm process, released in September 2019
Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Sunny Cove is used in the singular performance core (P-core) of Lakefield processors.[13] AVX and more advanced instruction sets are disabled due to the E-core not supporting them.
Ice Lake-SP: server-only successor to Cascade Lake, using 10 nm process, released in April 2021[5][14]
Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions.[19]
Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake; uses Intel 7 process (previously known as 10ESF),[20] released on November 4, 2021.[21] Golden Cove is used in P-cores of Alder Lake processors.[22]
Sapphire Rapids: server and workstation-only, successor to Ice Lake-SP, manufactured on Intel 7 process,[20][23] released on January 10, 2023. Introduces
AMX.
A refresh of Golden Cove with increased L2 and L3 caches and core clocks.
Raptor Lake: successor to Alder Lake with increased cache sizes, core clocks and the number of E-cores, released on October 20, 2022. Manufactured using Intel 7 process. Raptor Cove is used in the P-cores while the E-cores are still implemented using Gracemont microarchitecture.
10 nm
Atom microarchitecture iteration after Goldmont Plus.[26]
Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Tremont is used in efficiency cores (E-cores) of Lakefield processors.[13]
Jasper Lake: Celeron and Pentium Silver desktop and mobile processors, released in Q1 2021.
Elkhart Lake: embedded processors targeted at
IoT, released in Q1 2021.
Intel 7 process[20]Atom microarchitecture iteration after Tremont. First Atom class core with AVX and AVX2 support.
Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake, released on November 4, 2021. Gracemont is used in E-cores of Alder Lake processors.[22]
Raptor Lake: a refresh of Alder Lake, released on October 20, 2022.
enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements. The Montvale update added demand-based switching (
SpeedStep) and core-level
lockstep execution.
enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, an integrated memory controller, QuickPath Interconnect, and other improvements e.g. a more active SoEMT.
Itanium processor featuring an all-new microarchitecture.[27] 8 cores, decoupling in pipeline and in multithreading. 12-wide issue with partial out-of-order execution.[28]
multi-core in-order
x86-64 updated version of P5 microarchitecture, with wide
SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called
MIC (Many Integrated Core).