Fewer 1970s designs include execute instructions: the
Nuclear Data 812 minicomputer (1971) (XCT),[14] the
HP 3000 (1972) (XEQ),[15] and the Texas Instruments
TI-990 (1975)[16] and its microprocessor version, the
TMS9900 (1976) (X).[17] An execute instruction was proposed for the
PDP-11 in 1970,[18] but never implemented for it[19] or its successor, the
VAX.[20]
Modern instruction sets do not include execute instructions because they interfere with
pipelining,
prefetching, and other optimizations.[citation needed]
Semantics
The instruction to be executed, the target instruction, may be in a register or fetched from memory. Some architectures allow the target instruction to itself be an execute instruction; others do not.
The target instruction is executed as if it were in the memory location of the execute instruction. If, for example, it is a subroutine call instruction, execution is transferred to the subroutine, with the return location being the location after the execute instruction. However, some architectures implement variants of the execute instruction which inhibit branches.[1]
The System/360 supports variable-length target instructions. It also supports modifying the target instruction before executing it. The target instruction
must start on an even-numbered byte.[9]
The GE-600 series supports execution of two-instruction sequences, which must be
doubleword-aligned.[10]
Some architectures support an execute instruction which operates in a different
protection and address relocation mode. For example, the
ITS PDP-10 paging device supports a
privileged-modeXCTR 'execute relocated' instruction which allows memory reads, writes, or both to use the user-mode page mappings.[21] Similarly, the
KL10 variant of the PDP-10 supports the privileged instruction PXCT 'previous context XCT'.[22]
The execute instruction can cause several problems when one execute instruction points to another one and so on:
the processor may be uninterruptible for multiple
clock cycles if the execute instruction cannot be interrupted in the middle of execution;
similarly, the processor may go into an infinite loop if the series of execute instructions is circular and uninterruptible;
if the execute instructions are on different
swap pages, all of the pages need to be swapped in for the instruction to complete, which can cause
thrashing.
An execute target may contain a
hook for adding functionality or for debugging; it is normally initialized as a
NOP which may be overridden dynamically.
An execute target may change between a fast version of an operation and a fully traced version.[23][24][25]
Tracing, monitoring, and emulation
This may maintain a pseudo-
program counter, leaving the normal program counter unchanged.[1]
Executing dynamically generated code, especially when
memory protection prevents executable code from being writable.
Emulating self-modifying code, especially when it must be
reentrant or read-only.[18]
In the IBM System/360, the execute instruction can modify bits 8-15 of the target instruction, effectively turning an instruction with a fixed argument (e.g., a length field) into an instruction with a variable argument.
Privileged-mode execute instructions as on the KL10 are used by
operating system kernels to execute operations such as block copies within the virtual space of user processes.
^Rossman, George E. (December 1975). "A Course of Study in Computer Hardware Architecture". IEEE Computer. 8 (12): 44–63.
doi:
10.1109/C-M.1975.218835.
S2CID977792., p. 50