CoreConnect is a
microprocessorbus-architecture from
IBM for
system-on-a-chip (SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral
cores within standard and custom SoC designs. As a standard SoC
design point, it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a
device control register (DCR) bus. High-performance peripherals connect to the high-
bandwidth, low-
latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing
AMBA bus architecture, allowing reuse of existing SoC-components.
IBM makes the CoreConnect bus available as a no-fee, no-royalty architecture to tool-vendors, core IP-companies, and chip-development companies. As such it is licensed by over 1500 electronics companies such as
Cadence,
Ericsson,
Lucent,
Nokia,
Siemens and
Synopsys.
The CoreConnect is an integral part of IBM's embedded offerings and is used extensively in their
PowerPC 4x0 based designs. In the past,
Xilinx was using CoreConnect as the infrastructure for all of their embedded processor designs.
Processor Local Bus (PLB)
General processor local bus
Synchronous, nonmultiplexed bus
Separate Read, Write data buses
Supports concurrent Read, Writes
Multimaster, programmable-priority, arbitrated bus